Master Development, Purchasing and License Agreement between Intel Corporation and Marvell Semiconductor, Inc.

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Summary

This agreement, dated May 19, 2000, is between Intel Corporation and Marvell Semiconductor, Inc. It sets the terms for Intel to purchase certain Gigabit Phy chips from Marvell and for Marvell to develop and manufacture an integrated chip combining Marvell’s technology with Intel’s, which will be sold exclusively to Intel. Marvell may also use Intel as a manufacturing source for the integrated chip. The agreement outlines development responsibilities, support obligations, and product branding, with specific terms detailed in attached exhibits.

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EX-10.8 2 0002.txt EXHIBIT 10.8 1 INTEL CONFIDENTIAL EXHIBIT 10.8 MASTER DEVELOPMENT, PURCHASING AND LICENSE AGREEMENT BETWEEN INTEL CORPORATION AND MARVELL SEMICONDUCTOR, INC. This "Agreement" dated May 19, 2000 ("Effective Date") is by and between Marvell Semiconductor, Inc., a California corporation, and its Affiliates, ("Marvell") and Intel Corporation, a Delaware corporation, and its Affiliates, ("Intel"). RECITALS A. Marvell manufactures and sells, among other things, data storage channel controllers, Fast Ethernet Phy chips for switches and Gigabit Phy chips. Intel manufactures and sells, among other things, networking devices, including servers, network interface cards, routers, hubs, LAN switches, Ethernet controller chips, network silicon and network processors. B. The parties wish to set forth in this Agreement the terms and conditions under which, during the term of this agreement (i) Intel will have the right to purchase from Marvell certain physical layer chips known as Gigabit Phy chips; (ii) Marvell will integrate its Gigabit Phy chip with ***** and will manufacture and sell the Integrated Gb Silicon only to Intel; and (iii) Marvell may utilize Intel as a fab source for the Integrated Gb Silicon. AGREEMENT Now therefore in consideration of the covenants stated herein, and for other good and valuable consideration, the receipt and sufficiency of which the parties acknowledge, the parties agree as follows: 1. DEFINITIONS In addition to terms defined elsewhere in this Agreement, the following capitalized terms will have the following meanings: 1.1 "Affiliate" means any entity that is directly or indirectly controlled by, under common control with or that controls the subject entity, where control has the meaning ascribed to such term by the United States Securities and Exchange Commission. 1.2 "Change of Control" of a party shall be deemed to have occurred if: i) That party merges with or into a third party whether or not the party is the surviving entity following such merger and as a result of such merger holders of the party's securities prior to the merger beneficially hold less than 51% of the capital stock of the surviving entity of such merger; or ii) That party becomes a Subsidiary of a third party; or iii) A third party acquires all or substantially all of that party's assets. For the purposes of this definition of Change of Control, in connection with Marvell, "party" means Marvell Technology Group Ltd., a Bermuda corporation, or Marvell Semiconductor, Inc., or both. 1.3 "FCS" or First Customer Shipment means the date on which Intel first makes generally available for purchase Integrated Gb Silicon, which shall be on or about the date defined in Exhibit D, Attachment #3 at III-8, including additional time required for potential additional steppings of the Master Agreement Page 1 2 INTEL CONFIDENTIAL Integrated Gb Silicon required to meet the specifications defined in Exhibit D, as required by Attachment #3 at III-7 of Exhibit D. 1.4 "Integrated Gb Silicon" means a single chip in which the Intel ***** and the Marvell Gb Phy are integrated. 1.5 "Intel *****" means the Gigabit Ethernet ***** that Intel has developed. 1.6 "Intel ***** Technology" means the netlist, cell libraries, tools, test vectors, other documentation and specific deliverables from Intel to Marvell listed in Attachment #3 of Exhibit D for the Intel ***** that Marvell may reasonably need to integrate the Marvell Gb Phy with the Intel *****. Intel ***** Technology shall not be defined to include the Intel ***** design itself. 1.7 "Intellectual Property Rights" means, collectively, Patents, Trade Secrets, Copyrights, mask works and all other intellectual property rights and proprietary rights, excluding trademarks, whether arising under the laws of the United States or any other state, country or jurisdiction, now or hereafter existing. For purposes of this Agreement: (a) "Patents" means all patent rights and all right, title and interest in all letters patent or equivalent rights and applications, including any reissue, extension, division, continuation, or continuation-in-part applications throughout the world, now or hereafter existing; (b) "Trade Secrets" means all right, title and interest in all trade secrets and trade secret rights arising under common law, state law, federal law or laws of foreign countries, now or hereafter existing; and (c) "Copyrights" means all copyrights, and all right, title and interest in all copyrights, copyright registrations and applications for copyright registration, certificates of copyright and copyrighted interests throughout the world, and all right, title, and interest in related applications and registrations throughout the world, now or hereafter existing. 1.8 "***** or "*****" means a ***** on which the functionality of a ***** is integrated in the form a chip or chipset. 1.9 "*****" means *****. 1.10 "MFC" as it pertains to either the Marvell Gb Phy or the Integrated Gb Silicon shall have the respective meanings set forth on Exhibit A attached hereto. 1.11 *****" means the code name for the project that will manage and produce the Integrated Gb Silicon. 1.12 *****" means a ***** that connects a ***** or other computing device to a network. 1.13 "Marvell Gigabit Phy" or "Marvell Gb Phy" means the stand-alone Ethernet physical layer chip developed by Marvell designed to operate at Gigabit speed, otherwise known as the "Alaska(TM)" Chip and all fixes and revisions to such chip or updates with substantially similar architecture thereto. 1.14 "Marvell Integration Technology" means the cell libraries, technical documentation and specific deliverables from Marvell to Intel listed in Attachment #3 of Exhibit D that Intel may reasonably need to convert Intel ***** elements to permit Marvell to make the Integrated Gb Silicon. Marvell Integration Technology shall not be defined to include the Marvell Gb Phy design itself. 1.15 "Phy" means physical layer device. 1.16 "SOW" means statement of work, a document that reflects a project or set of projects to be undertaken by both parties. 1.17 "Subsidiary" means with respect to a party any corporation, partnership or other entity, now or hereafter existing, (i) more than percent (50%) of whose outstanding shares or securities entitled to vote for the election of directors or similar managing authority is directly or indirectly owned or controlled by such party or (ii) that does not have outstanding shares or securities but more than fifty percent (50%) of whose ownership interest representing the right to make the decisions for such entity is directly or indirectly owned or controlled by such party. Master Agreement Page 2 3 INTEL CONFIDENTIAL 1.18 "Support" means telephone, e-mail and on-site consultation/support, plus notification of and access to Updates, all as more specifically set forth in attached Exhibit F. 1.19 "Updates" means bug fixes, additional performance improvements, cost and/or power reduction enhancements. 2 PURCHASE RIGHTS; SUPPORT; PRODUCT MARKINGS 2.1 Purchase Rights. During the term of this Agreement, Intel will have the right to purchase from Marvell Gb Phys and Integrated Gb Silicon on the terms and conditions set forth in Exhibit A and Exhibit B. 2.2 Support. Marvell shall provide Support to Intel on the terms and conditions as set forth in Exhibit F. 2.3 Product Marking. The Integrated Gb Silicon will be marked and branded as an Intel part, as set forth in Exhibit E. 3 DEVELOPMENT OF INTEGRATED GB SILICON 3.1 Marvell agrees to use commercially reasonable efforts to develop the Integrated Gb Silicon on the timetable and otherwise in accordance with the SOW attached as Exhibit D. Intel agrees to provide to Marvell the Intel ***** Technology as set forth in the SOW for the purposes of completing such development. In addition, upon Intel's written request, Marvell agrees to use commercially reasonable efforts to develop an enhanced version of the Integrated Gb Silicon based on next generation Intel ***** Technology based on a new SOW, which will be developed and agreed upon by both parties for *****, assuming the ***** and the ***** NRE and QA conformance expenses. 3.2 Subject to the rights to terminate for convenience provided for in Section 11 hereof, Intel agrees to use its commercially reasonable efforts to achieve volume sales of the Integrated Gb Silicon. 4 OWNERSHIP; LICENSES; RESTRICTIONS 4.1 Ownership. (a) Separate Ownership. Marvell retains ownership of the Marvell Integration Technology (and all Intellectual Property Rights therein) and all portions of the Integrated Gb Silicon separately developed by Marvell (and all Intellectual Property Rights therein) and Intel will retain ownership of the Intel ***** Technology (and all Intellectual Property Rights therein) and all portions of the Integrated Gb Silicon separately developed by Intel (and all Intellectual Property Rights therein). (b) Joint Ownership (Other than of Patentable Inventions). Other than with respect to jointly developed patentable inventions (which are addressed below), Intel and Marvell will jointly own any portion of the Integrated Gb Silicon (and all Intellectual Property Rights therein) that is jointly developed in such a manner that, under applicable law, the rights therein (including Intellectual Property Rights therein) are jointly owned, but with no rights of accounting therefor. With respect to copyrightable works, the parties do not intend that their contributions be merged into inseparable or interdependent parts of a unitary whole so that joint copyright ownership results. To the extent necessary to effect such joint ownership, each party hereby assigns to the other party an equal and undivided one-half interest in any such jointly developed technology (and all Intellectual Property Rights, excluding Patent rights, therein.) Each party agrees to cooperate with the other and to execute any document reasonably necessary to carry out the intent of this Section, including developing a list of any jointly developed Patentable Inventions, which the parties agree shall be the sole and definitive source to document the existence of any such jointly owned Patentable Inventions. (c) Patentable Inventions. (i) Filing. To the extent there are any patentable inventions jointly developed hereunder, if the invention relates primarily to a Gigabit Phy chip, Marvell will have the first option Master Agreement Page 3 4 INTEL CONFIDENTIAL to file the patent application thereon under its own name. If the invention relates primarily to a ***** chip, Intel will have the first option to file the patent application thereon under its own name. If the relevant party does not exercise its rights thereunder within the earlier of six months or 30 days before any applicable statutory bar date, the other party shall have the right to file such applications at its own expense. The filing party shall, at its own cost and subject to commercially reasonable efforts, use outside counsel to prosecute such applications to obtain the broadest possible coverage permitted by law, and shall permit the other party an opportunity to review and comment on any such application prior to filing. No application shall be permitted to issue or go abandoned without providing the other party an opportunity to review the application and its prosecution history. In the event the filing party elects an application to finally go abandoned, the other party shall be given notice of such decision and shall thereafter have the opportunity to take over prosecution of such application at its own expense. (ii) Ownership; Licenses under such Patents. The filing party shall be the owner of record for any such application and the other party shall have a fully paid-up, world-wide, nonexclusive irrevocable license under any Patents which may issue thereunder to make, use, have made, sell and offer for sale, and import any product or service anywhere in the world. 4.2 Licenses. (a) License to Marvell. Intel hereby grants to Marvell, under all of Intel's Intellectual Property Rights embodied in the Intel ***** Technology, a non-exclusive, nontransferable, nonsublicensable, royalty-free, revocable (for material breach under Section 11.4 hereof) worldwide license (i) to internally use, copy, have copied, modify and have modified the Intel ***** Technology solely for the purposes of developing and supporting the Integrated Gb Silicon solely for the benefit of Intel (ii) and to manufacture, have manufactured and sell only to Intel the Integrated Gb Silicon. In no event may Marvell exercise the foregoing license to develop, make, use, sell or otherwise distribute any Intel ***** Technology other than for Intel's benefit. Marvell will have no right to make or use Integrated Gb Silicon chips for its own use, or to sell them to anyone other than Intel. The parties acknowledge that nothing in the foregoing is intended to restrict Marvell from testing and validating Integrated Gb Silicon chips to the extent necessary for the purpose of fulfilling its obligations hereunder. (b) License to Intel. Marvell hereby grants to Intel under all of Marvell's Intellectual Property Rights embodied in the Marvell Integration Technology, a non-exclusive, nontransferable, nonsublicensable, royalty-free, revocable (for material breach under Section 11.4 hereof) worldwide license to internally use, copy, have copied, modify and have modified the Marvell Integration Technology solely for the purposes of converting Intel ***** elements to such form as may be required for Marvell to develop and manufacture the Integrated Gb Silicon. In no event may Intel exercise the foregoing license to develop, make, use or sell, or otherwise distribute any Marvell Integration Technology other than for the foregoing purpose. (c) Restriction. From the Effective Date through the end of the second calendar quarter after FCS (the "Restriction Period"), Marvell agrees not to deliver or license any of the Marvell Integration Technology to any external third party under an agreement that would permit the third party to integrate the Marvell Integration Technology with a ***** for the purposes of developing a *****, and further agrees during the Restriction Period not to design or otherwise enter into any work on any chip that integrates a Marvell Gigabit Phy with a ***** for the purpose of developing a ***** other than with Intel. Intel shall provide Marvell with one-year prior written notice in the event Intel plans to ship an equivalent Integrated Gb Silicon device. Upon the receipt by Marvell of such notice from Intel, the terms of restriction against Marvell set forth in this Section 4.2(c) shall be of no further force or effect. (d) Have Made Rights. For purposes of exercising its have made rights granted under Section 4.2(a), Marvell may deliver Intel ***** Technology only to those subcontractors approved in advance in writing by Intel, which approval shall not be unreasonably withheld. For the purposes of exercising its have made rights granted under Section 4.2(b), Intel may deliver Marvell Integration Technology only to those subcontractors approved in advance in writing by Marvell, Master Agreement Page 4 5 INTEL CONFIDENTIAL which approval shall not be unreasonably withheld, and then only for the purpose of completing Intel's obligations hereunder, subject to the further following provisions: (i) Intel may deliver to a subcontractor only those portions of the Marvell Integration Technology necessary for the subcontractor to complete the relevant subcontracted project. (ii) The subcontractor and any employee of such subcontractor working on the subcontracted project shall be obligated to maintain the confidentiality of the Marvell Integration Technology on terms substantially as restrictive as the confidentiality provisions of the CNDA identified in this Agreement and may use the Marvell Integration Technology solely for the purposes of completing the subcontracted project. (iii) Prior to starting the subcontracted project, the subcontractor and any employee of such subcontractor working on the subcontracted project must each sign a confidentiality agreement in a form approved in advance by Marvell. (e) Fab Limitations. Marvell shall have the Integrated Gb Silicon manufactured only at TSMC or at such other fab as the parties may mutually agree upon in writing. (f) Future Rights to Manufacture. Upon Intel's advanced written request, but no sooner than 1-calendar year after FCS, Marvell agrees to enter into good faith negotiations to consider utilizing an Intel fab for the manufacture of the Integrated Gb Silicon, provided that Intel's wafer cost is materially lower than that of TSMC's (or other approved fab's) and provided further that Intel's design rules and electrical parameters are substantially similar to those of TSMC's (or other approved fab's) to justify the porting of the design to such Intel fab. 5 CONFIDENTIALITY 5.1 Confidentiality and Information Exchange. The parties acknowledge and agree that the Intel ***** Technology and the Marvell Integration Technology constitute the Confidential Information of the disclosing party. Except to the extent disclosure is permitted for have made rights under Section 4.2(d) hereof, each party agrees to maintain the confidentiality of the other's Confidential Information, as well as any jointly owned technology, as described in Section 4.1(b), subject to and in accordance with the terms and conditions of the form of Corporate Non- Disclosure Agreement between the parties, number #***** dated ***** (the "CNDA"), the terms of which are incorporated herein by this reference, and in accordance with the terms of this Agreement. The parties agree that any of the foregoing information shall be deemed Confidential Information without the need for express identification under the requirements of CNDA, and that no CITR is required. 5.2 Confidentiality Regarding Agreement. (a) The parties agree that except as may be required by law, regulation, direction of any governmental or judicial or administrative agency, and except as otherwise expressly permitted by this Section 5.2, any disclosure of the existence of or any of the terms or the exhibits of this Agreement or the relationship between the parties shall be made only with the prior written agreement of both parties. (b) The parties agree that they shall cooperate in good-faith to accommodate the interests of each party in obtaining confidential treatment of the terms and conditions of this Agreement and the exhibits hereto from the U.S. Securities and Exchange Commission (the "SEC") in connection with the Company's initial public offering of its shares of Common Stock (the "IPO") pursuant to the Securities Act of 1933, as amended, (the "Act"). (c) Notwithstanding anything to the contrary set forth herein, nothing in this Section 5 shall be deemed to provide Intel with an independent right to block, stop, slow or otherwise prevent or hinder the Company's IPO. Master Agreement Page 5 6 INTEL CONFIDENTIAL (d) Marvell agrees that it will provide Intel with drafts of any documents or other filings in which Marvell is required to disclose this Agreement or any other confidential information subject to the terms of this Agreement. With respect to such documents and filings, other than filings with the SEC in connection with Marvell's IPO, Marvell shall deliver such drafts to Intel at least ***** business days prior to the filing or disclosure thereof and will make any changes to such materials as reasonably requested by Intel to the extent permitted by law or any rules or regulations of the SEC, or any other relevant regulatory agency, as applicable. Notwithstanding the foregoing, in connection with Marvell's IPO, (i) if confidential treatment is requested by Intel, Marvell agrees to file with the SEC a request for confidential treatment in form and substance reasonably satisfactory to Intel and to use its commercially reasonable efforts in responding to any SEC comments to obtain confidential treatment of such items as Intel may request, (ii) Marvell shall cooperate with Intel in seeking such confidential treatment, including allowing Intel to participate in any telephonic conferences or other communications relating to such confidential treatment with the SEC and (iii) Marvell shall provide Intel with the opportunity to review and comment on the initial request during the preparation thereof and the responses to any SEC comments relating thereto, and for this purpose Marvell (A) shall provide to Intel any such response of the SEC to such request for confidential treatment within a reasonable period of time after receipt thereof, but in no event more than ***** business day following such receipt and (B) shall allow Intel a reasonable period of time (not to exceed *****) business days (or ***** business day if the SEC response is received by Marvell on or after the last day of the road show with respect to the Marvell IPO)) after receiving such response from Marvell to respond thereto. The parties agree that Marvell cannot guarantee that the SEC will grant any request for confidential treatment. Subject to compliance with the provisions of this paragraph (d), Marvell may disclose in its registration statement on Form S-1 filed in connection with its IPO and in the exhibits thereto such information, including filing such portions of this Agreement and the exhibits hereto as the SEC may require, following exhaustion of the confidential treatment procedure. For the purposes of this paragraph (d), the term "exhaustion of the confidential treatment procedure" shall mean that the examiner at the SEC has informed Marvell that it will be unable to declare Marvell's registration statement effective at the time requested by Marvell unless Marvell complies with the SEC's requirements as to limitation of confidential treatment and Marvell has notified Intel within ***** business day as provided for above. After Marvell has been so informed by the examiner at the SEC and after Intel has had ***** business day to respond thereto as provided for above, Marvell shall have the sole authority to determine whether or not to comply with the SEC's response. Marvell will not file this Agreement or the exhibits with any governmental authority or any regulatory body, or disclose the identity of Intel in any filing except as permitted above. 6 WARRANTIES THE PARTIES MAKE NO WARRANTIES, EITHER EXPRESS OR IMPLIED, WITH RESPECT TO ANY DELIVERABLES INCLUDING THE INTEL ***** TECHNOLOGY AND THE MARVELL INTEGRATION TECHNOLOGY ("THE DELIVERABLES"). THE PARTIES SPECIFICALLY DISCLAIM THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT OF ANY INTELLECTUAL PROPERTY RIGHT OF ANY THIRD PARTY. THE DELIVERABLES ARE PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND. 7 INDEMNIFICATION 7.1 Generally. Within the limitations set out in Section 7.2, either party ("Indemnitor") will defend or settle any suit or proceeding brought against the other (the "Indemnitee") based upon a claim that Indemnitee's use or distribution of any of Indemnitor's technology (Intel ***** Technology or Marvell Integration Technology, as relevant) ("Indemnified Technology") as authorized hereunder and in the form provided hereunder infringes or misappropriates the Intellectual Property Rights of a third party, and the Indemnitor will pay the damages and costs finally awarded against Indemnitee up to such limits, so long as: (i) Indemnitor is notified promptly in writing of such claim (provided that the failure to give such notice shall only relieve Indemnitor of its indemnity obligations hereunder if and to the extent that such failure materially prejudices Indemnitor), or (ii) Master Agreement Page 6 7 INTEL CONFIDENTIAL Indemnitor controls the defense and settlement of the claim, and (iii) Indemnitee cooperates reasonably, and gives all necessary authority, information and assistance to Indemnitor. Notwithstanding the foregoing, an Indemnitor is not obligated to defend or settle any such suit and is not obligated to pay any such damages or costs, if such claim arises out of (i) a combination of the Indemnified Technology with technology not supplied by the Indemnitor, except where such has no noninfringing use other than in such combination; (ii) a modification, alteration or amendment of the Indemnitor's Indemnified Technology. The Indemnitee shall use commercially reasonable efforts to modify and replace any products that are alleged to be infringing. 7.2 Limitations. Indemnitor shall not be responsible for any costs, expenses or compromise incurred or made by Indemnitee without Indemnitor's prior written consent. If a suit or other proceeding has been filed, or it reasonably appears that one will be filed or that an injunction shall issue, Indemnitor shall promptly give written notice thereof to Indemnitee. Indemnitor may, in its sole discretion and at its own expense, procure for Indemnitee the right to continue using the Indemnified Technology, replace it with a non-infringing technology or modify it so that it becomes non-infringing. 7.3 Exclusive Remedy. Except with respect to any indemnification obligations the parties may have under the Purchasing Terms attached as Exhibit B, the foregoing states the entire obligation and exclusive remedy of each of the parties hereto with respect to any alleged infringement of the Intellectual Property Rights of any third party by any product, technology or software furnished hereunder. 8 LIMITATION OF LIABILITY AND LIABILITY CAP 8.1 Limitation. A PARTY'S LIABILITY HEREUNDER SHALL BE LIMITED TO DIRECT, OBJECTIVELY MEASURABLE DAMAGES. IN NO EVENT SHALL EITHER PARTY HAVE ANY LIABILITY FOR ANY INDIRECT OR SPECULATIVE DAMAGES (INCLUDING, WITHOUT LIMITING THE FOREGOING, PUNITIVE, CONSEQUENTIAL, INCIDENTAL AND SPECIAL DAMAGES) INCLUDING, BUT NOT LIMITED TO, LOSS OF USE, BUSINESS INTERRUPTIONS AND LOSS OF PROFITS, IRRESPECTIVE OF WHETHER THE PARTY HAS ADVANCE NOTICE OF THE POSSIBILITY OF ANY SUCH DAMAGES. THE PARTIES ACKNOWLEDGE THAT THESE LIMITATIONS ON POTENTIAL LIABILITIES WERE AN ESSENTIAL ELEMENT IN SETTING CONSIDERATION UNDER THIS AGREEMENT. 8.2 Liability Cap. IN NO EVENT SHALL EITHER PARTY'S LIABILITY UNDER THIS AGREEMENT EXCEED THE GREATER OF $200 MILLION OR THE AMOUNT PAID BY INTEL HEREUNDER. THE PARTIES AGREE THAT THE FOREGOING LIMIT SHALL NOT APPLY TO ACTIONS BY A PARTY FOR VIOLATIONS OF SUCH PARTY'S INTELLECTUAL PROPERTY RIGHTS (AS SUCH RIGHTS ARE DEFINED IN SECTION 1.7 HEREOF) BY THE OTHER PARTY. 9 DISPUTE RESOLUTION. All disputes arising directly under the express terms of this Agreement or the grounds for termination thereof shall be resolved as follows: First, the senior management of both parties shall meet to attempt to resolve such disputes. If the disputes cannot be resolved by the senior management, either party may make a written demand for formal dispute resolution. Within thirty (30) days after such written notification, the parties agree to meet for one day with an impartial mediator and consider dispute resolution alternatives other than litigation. If an alternative method of dispute resolution is not agreed upon within thirty (30) days after the one-day mediation, either party may begin litigation proceedings. 10 AUDIT RIGHTS Each party agrees to make and to maintain until the expiration of two (2) years after the period to which they pertain, (i.e. during the time Option #2 pricing in Exhibit A is utilized or during purchase of the stand-alone Marvell Gb Phy), sufficient books, records and accounts regarding each party's manufacturing and sales activities, including but not limited to setting of the ASP by Intel or the Marvell Product Cost by Marvell in accordance with Exhibit A, in order to confirm accurate Master Agreement Page 7 8 INTEL CONFIDENTIAL calculation of compensation hereunder and thereunder. A party shall have the right, upon reasonable notice, during the other party's normal business hours, and not more than once every twelve (12) months during the term hereof and upon termination of this Agreement (and one-year thereafter) and upon completion of all product deliveries and sales hereunder of the Marvell Gb Phy and the Integrated Gb Silicon, to appoint a nationally recognized certified public accountant reasonably acceptable to the other party who agrees to be bound to confidentiality protections acceptable to such other party to examine such books, records and accounts, to verify such party's reports on the amount of payments made to the other party under this Agreement. Such auditor shall be instructed to report only as to whether there is a discrepancy and if so, the amount of such discrepancy. If any such examination discloses a shortfall or overpayment in the fees due to the party, the appropriate party shall reimburse the other party for the full amount of such shortfall or overpayment. Moreover, in the event the amount of shortfall or overpayment exceeds the greater of $50,000 or 5% of the amount due or paid, as the case may be, during the period under review, the non-auditing party shall reimburse the auditing party for the cost and expenses incurred in connection with such audit. 11 TERM AND TERMINATION 11.1 Term. Unless earlier terminated or extended on the terms of this Section 11, this Agreement will expire two years after the Intel FCS of the Integrated Gb Silicon. The Purchasing Terms shall survive for two years after expiration of this Agreement. 11.2 Extension. By mutual written agreement, delivered at least 30 days before the end of the Agreement, the parties may seek to extend this Agreement. 11.3 Termination for Convenience. (a) At anytime after FCS, Intel may terminate this Agreement without cause at any time upon 1-year advance written notice to Marvell. During such 1-year notice period, Intel shall be required to purchase from Marvell 100% of Intel's volume requirements for any single chip device in which a ***** and a Gigabit Phy are integrated. (b) Upon 30 days written notice to Marvell, Intel may terminate this Agreement without cause, upon the failure to complete ***** of the Integrated Gb Silicon within 60 days after the milestone date set forth at item II-20 in Attachment #3 in the attached Exhibit D for achieving the ***** or no later than *****. (c) Upon 30 days written notice to Marvell, Intel may terminate this Agreement without cause, upon the failure to complete FCS of the Integrated Gb Silicon within 60 days after the milestone date set forth in item III-8 in Attachment #3 in the attached Exhibit D or no later than *****. (d) Notwithstanding Section 11.3 (c), once a "Go" decision has been made by Intel and Marvell to proceed in accordance with the acceptance requirements of item III-6 of Attachment #4 from Exhibit D, Intel shall: (i) be required to complete *****; (ii) be required to purchase from Marvell 100% of Intel's volume requirements for any single chip device in which a ***** and a Gigabit Phy are integrated as provided for in Section 3 of Exhibit A; and, (iii) not be permitted to terminate this Agreement under Section 11.3 (c) above. (e) Upon delivery of a notice of a termination for convenience pursuant to this Section 11.3, the terms and conditions of restriction against Marvell set forth in Section 4.2(c) hereof shall be of no force or effect. 11.4 Termination for Cause. Subject to the parties exhaustion of the dispute resolution process through mediation as set forth in Section 9, either party may thereafter terminate this Agreement if: 11.4.1 the other party breaches any material provision of this Agreement (for purposes of this Agreement, a failure to pay any material amounts owing shall be considered a material breach) and fails to remedy such breach within thirty (30) days after the receipt by the breaching party of the non-breaching party's written notice of such breach (or, if such breach cannot be remedied in Master Agreement Page 8 9 INTEL CONFIDENTIAL that time, failure to commence remedial procedures reasonably satisfactory to the non-breaching party within such 30-day time frame); or 11.4.2 the other party dissolves, becomes insolvent or makes a general assignment for the benefit of its creditors; or 11.4.3 a voluntary or involuntary petition or proceeding is commenced by or against the other party under the Federal Bankruptcy Act or any other statute of any state or country relating to insolvency or the protection of the rights of creditors, or any other insolvency or bankruptcy proceeding or other similar proceeding for the settlement of the other party's debt is instituted; or 11.4.4 A receiver of all or substantially all of the property of the other party is appointed. Except as expressly limited by this Agreement, termination of this Agreement under this Section 11 will be without prejudice to any other remedy that may be available to a party under applicable law. 11.5 Notification and Change of Control 11.5.1 Unless illegal under applicable law, rule, regulation, dictate, mandate or release of a governmental or regulatory agency with jurisdiction over such transaction, Marvell shall provide Intel with written notice of any unsolicited offer (written or oral) from any third party for a proposed Change of Control, which Marvell is seriously considering or plans to seriously consider, as evidenced by a resolution of Marvell's Board of Directors to such effect. Any such notice shall be delivered to Intel as soon as reasonably practicable and without delay. Such notice shall set forth the identity or identities of the third party involved, so long as such disclosure is not illegal under applicable law rule, regulation, dictate, mandate or release of a governmental or regulatory agency with jurisdiction over such transaction. 11.5.2 Not later than thirty (30) days from the announcement of an intended Change of Control, Marvell shall use commercially reasonable efforts to have an officer of the acquiring company (1) send a written confirmation to Intel that the acquiring company shall support its contractual obligations and (2) meet with Intel management to discuss the transition and commitment to the Marvell obligations. 11.5.3 In connection with a Change of Control, Intel will retain a right to cancel any applicable SOW(s) without further obligations (other than paying for that portion of the phase which is not then complete) and a right to assign the Agreement pursuant to Section 12.7. 11.5.4 Following a Change in Control, during any period of time that development work is occurring under a SOW, Intel will have the right to approve of ***** in the project, which such approval shall not be unreasonably withheld. Intel's basis for the rejection of a proposed change by Marvell in ***** may be based on the ***** qualifications only. 11.5.5 Notwithstanding anything to the contrary set forth herein, nothing in this Section 11.5 shall be deemed to provide Intel with an independent right to block, stop, slow or otherwise prevent or hinder a Change of Control Transaction. 11.6 Survival. The parties' rights and obligations under Sections 1, 2; 4.1; 4.2(a)(but only to the extent necessary to support Marvell's obligations under Section 2, if any); 4.2(c) (unless already expired by its terms); 5; 6; 7; 8; 9; 10 (to the extent set forth therein); 12 (except for 12.1, if it has expired by its terms) will survive any expiration or termination of this Agreement. 12 GENERAL PROVISIONS 12.1 *****. During the term of this Agreement, neither party shall ***** any networking technical, marketing or sales *****, if such technical, marketing or sales ***** pursuant to this Agreement, for Master Agreement Page 9 10 INTEL CONFIDENTIAL the purpose of *****. In the event any such ***** in response to a ***** or ***** which was not instructed to ***** shall provide notice of such ***** to the other within thirty days after such *****. 12.2 Notice. Unless otherwise agreed to by the parties, all notices required under this Agreement shall be deemed effective when received and made in writing by either (i) registered mail, (ii) certified mail, return receipt requested, or (iii) overnight mail, addressed and sent to the attention: --------------------------------------------------------------------- For Marvell: For Intel Marvell Semiconductor, Inc. Intel Corporation Attn: Chief Executive Officer 2200 Mission College Blvd 645 Almanor Avenue Santa Clara, CA 95052 Sunnyvale, CA 94086 Attention: General Counsel With a copy to: With a copy to: Marvell Semiconductor, Inc. Intel Corporation Attn: General Counsel Mail Stop JF3-149 645 Almanor Avenue 2111 NE 25th Avenue Sunnyvale, CA 94086 Hillsboro, Oregon 97214 Attn: Post Contract Management --------------------------------------------------------------------- Either party may give written notice of a change of address and, after notice of such change has been received, any notice or request shall thereafter be given to such party at such changed address. 12.3 Payment Address: Payments to be made hereunder shall be addressed and sent to the attention: ---------------------------- For Marvell: Marvell Semiconductor, Inc. 645 Almanor Avenue Sunnyvale, CA 94086 ---------------------------- Either party may give written notice of a change of address and, after notice of such change has been received, any notice or request shall thereafter be given to such party at such changed address. For the purposes of administering the Gross Margin Sharing, Marvell will provide the address for the packaging house at a later date. 12.4 Independent Contractor. Each party is and shall remain an independent contractor with respect to all performance rendered pursuant to the terms of this Agreement and exhibits hereto. Neither party nor any employee thereof shall be considered an employee or agent of the other party for any purpose and shall have no authority to bind or make commitments on behalf of such other party for any purpose and shall not hold itself or themselves out as having such authority. Nothing within this Agreement shall be construed as establishing a partnership, joint venture, or any other entity jointly owned or controlled by the parties. 12.5 Compliance with Laws. Each party shall, at its own expense, comply with any governmental law, statute, ordinance, administrative order, rule or regulation relating to its duties, obligations and performance under this Agreement and the exhibits hereto and shall procure all licenses and pay all fees and other charges required thereby. 12.6 Force Majeure. Neither party shall be held liable for failure to fulfill its obligations other than payment obligations under this Agreement, if the failure is caused by flood, extreme weather, or other acts of God or natural calamity, fire, theft, war, riot, embargo, earthquake, acts of Master Agreement Page 10 11 INTEL CONFIDENTIAL governmental agency or military authority, or similar causes beyond the control of such party, and the term for performance shall be increased to a reasonable period of time. 12.7 Assignment. Neither party may sell, transfer, assign, or delegate in whole or in part this Agreement, or any rights, duties, obligations or liabilities under this Agreement, without the prior written consent of the other party. Notwithstanding the foregoing, this Agreement may be assigned in the event of a Change of Control. Certain notice and other obligations must be met in the event of a Change of Control, as set forth in Section 11.5 above. This Agreement will inure to the benefit of and be binding upon each party's permitted successors and assigns. 12.8 Governing Law; Personal Jurisdiction and Venue. Any claim arising under or relating to this Agreement shall be governed by the internal substantive laws of the State of California or federal courts located in California, without regard to principles of conflict of laws. Each party hereby agrees to personal jurisdiction and venue in the courts of the State of California, county of Santa Clara for all disputes and litigation arising under or relating to this Agreement. 12.9 No Other Rights. This Agreement shall not be construed to grant any rights by implication, estoppel, or otherwise, that are not granted through its express provisions. 12.10 Severability. If any provision of this Agreement is held by a court of competent jurisdiction to be contrary to law, the remaining provisions of this Agreement will remain In full force and effect and shall be interpreted, to the extent possible, to achieve its purposes without the invalid, illegal or unenforceable provision. 12.11 Duplicate Originals. This Agreement shall be executed in duplicate originals, which shall constitute one Agreement. 12.12 Entire Agreement. This Agreement constitutes the entire agreement between the parties and supersedes all prior and contemporaneous agreements, oral or written, and all other communications relating to the subject matter of this Agreement. Any terms contained in purchase orders, invoices, acknowledgments, shipping instructions, or other forms shall be void and of no effect. 12.13 Modification. No alteration, amendment, waiver or any other change in any term or condition of this Agreement will be valid or binding on either party unless such has been mutually assented to in writing by authorized representatives of both parties. 12.14 Waiver. The failure of either party to enforce at any time any of the provisions of this Agreement, or the failure to require at any time performance by the other party of any of the provisions of this Agreement, shall in no way be construed to be a present or future waiver of such provisions, nor in any way affect the right of either party to enforce each and every such provision thereafter. The express waiver by either party of any provision, condition or requirement of this Agreement shall not constitute a waiver of any future obligation to comply with such provision, condition or requirement or constitute a waiver of any other provision of this Agreement. 12.15 Export. Neither party shall export, either directly or indirectly, any product, service or technical data or system incorporating such Items without first obtaining any required license or other approval from the U. S. Department of Commerce or any other agency or department of the United States Government. In the event any product is exported from the United States or re-exported from a foreign destination by either party, that party shall ensure that the distribution and export/re-export or import of the product is in compliance with all laws, regulations, orders, or other restrictions of the U.S. Export Administration Regulations and the appropriate foreign government. Both parties agree that neither it nor any of its subsidiaries will export/re-export any technical data, process, product, or service, directly or indirectly, to any country for which the United States government or any agency thereof or the foreign government from where it is Master Agreement Page 11 12 INTEL CONFIDENTIAL shipping requires an export license, or other governmental approval, without first obtaining such license or approval. 12.16 Taxes. All applicable taxes and other charges such as duties, customs, tariffs, imposts, and government imposed surcharges shall be stated separately within invoices and each party shall be responsible for the payment of such taxes and other charges for which it is legally responsible. In the event that a party is prohibited by law from remitting payments unless it deducts or withholds taxes therefrom on behalf of the local taxing jurisdiction, then that party shall duly withhold such taxes and shall remit the remaining net invoice amount to the other party. IN WITNESS WHEREOF, the parties have executed this Agreement as of the Effective Date. INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: _________________________________ By:_________________________________ Printed Name: _______________________ Printed Name: ______________________ Title: ______________________________ Title: _____________________________ Date: _______________________________ Date: ______________________________ EXHIBITS: Exhibit A Compensation Exhibit B Purchasing Terms Exhibit C Purposely Blank Exhibit D Statement of Work for ***** Exhibit E QA Requirements Exhibit F Support Requirements Master Agreement Page 12 13 INTEL CONFIDENTIAL EXHIBIT A - COMPENSATION 1) GENERALLY. Intel will purchase from Marvell the Marvell Gb Phy and Integrated Gb Silicon under the purchasing terms in Exhibit B. The prices paid for such products are specified below in this Exhibit A. A) MFC - MARVELL GB PHY. Marvell agrees that the price it charges to Intel for a stand-alone Marvell Gb Phy will not be more than that price that Marvell has charged or will charge any other customer for the same product, MFC, provided that: i) The Marvell Gb Phy represents ***** or greater of Gigabit Phy unit shipments by Intel in the prior calendar quarter. B) MFC - INTEGRATED GB SILICON. Marvell agrees that the price it charges to Intel for the Integrated Gb Silicon will not be more than that price Marvell has charged or will charge any other customer for the same or equivalent product with a ***** size and *****, MFC, provided that: i) The Integrated Gb Silicon represents *****% of Integrated *****/Phy unit shipments by Intel in the prior calendar quarter. c) If Marvell provides lower pricing to another customer as set forth above, then Intel shall pay such lower price. Intel will be credited for any excess amount it paid or will pay from the date such customer paid the more favorable price until the termination of such favorable pricing. 2) INTEL PURCHASE OF MARVELL GB PHY a) Intel can purchase from Marvell a fully packaged, validated, tested and standards-compliant stand-alone Marvell Gb Phy. b) Starting in Q4 2000+, Intel will pay per unit prices based on the schedule provided below, where the volume percentage indicates the percentage that the Marvell Gb Phy represents out of all Gigabit Phys expected to be purchased by Intel during such calendar quarter. The provisions of this Section 2 b) of this Exhibit A shall be subject to the Audit Rights provisions of Section 10 of the main text of the Agreement and prices will be adjusted as appropriate to reflect actual purchases. Intel will pay per unit prices for Q2 2000 and Q3 2000 as set forth in Table 1 below,*****. TABLE 1
VOLUME PERCENTAGE Q2 2000 Q3 2000 Q4 2000+ - ----------------------------- --------------------------- -------------------------- --------------------------- 0-*****% $*****.00 $*****.00 $*****.00 *****%-*****% $*****.00 $*****.00 $*****.00 *****%-*****% $*****.00 $*****.00 $*****.00 *****%+ $*****.00 $*****.00 $*****.00
c) This schedule represents the maximum per unit amount Intel will pay Marvell. d) The parties agree to review pricing on a quarterly basis. Compensation Page 1 14 INTEL CONFIDENTIAL 3) INTEL PURCHASE OF INTEGRATED GB SILICON Intel will be required to purchase from Marvell 100% of Intel's volume requirements for any single chip device in which a ***** and a Gigabit Phy are Integrated from the Effective Date through one year after FCS and up to and through the one-year notification period following Intel's delivery of a notice to Marvell of Intel's plan to ship an equivalent Integrated device provided for in Section 4.2(c) of the main text of the Agreement. In any calendar quarter of the term of this Agreement, Intel will have the choice to purchase at a predetermined price set forth below in Table 2 ("Option #1"), or to purchase under the ***** margin sharing model defined below (Option #2). Once Intel chooses Option #2, Intel cannot return to Option #1. Nothing herein shall be deemed to constitute the parties as partners or to create a joint venture relationship between the parties. At all times hereunder, the parties agree that their relationship shall be that of customer and supplier. At its own expense, Intel may order the production of risk wafers to accelerate Intel's receipt by Marvell of a final production sample of the Integrated Gb Silicon. A) OPTION #1: PREDETERMINED PRICE Intel will purchase from Marvell, a fully packaged, validated and tested Integrated Gb Silicon as specified below in Table 2: TABLE 2
- -------------- ----------- ------------ ----------- ------------ ----------- ------------ ------------ Q1 `01 Q2 `01 Q3 `01 Q4 `01 Q1 `02 Q2 `02 Q3 `02 Q4 `02 $***** $***** $***** $***** $***** $***** $***** $*****
i) This schedule represents the per-unit amount Intel will pay Marvell for any given quarter under Option #1. ii) If Marvell does not meet major milestones set forth in Table 3 below and item II-20 from Attachment 3 to Exhibit D, excluding delays caused by Intel, the per-unit amount will be***** on this schedule. iii) Detailed purchasing terms (lead times, QA, shipping, etc), are found in Exhibits B and E. iv) These prices assume that Marvell integrates the Intel ***** with the specifications set forth in Exhibit D together with an on-chip SRAM no larger than ***** and a package equal in cost to a typical ***** package type. In the event the actual package cost exceeds the cost of a typical ***** package type, the price paid in accordance with Table 2 above shall be increased by such amount. In the event, the actual package cost is less than the cost of a typical ***** package type, the price Intel paid in accordance with Table 2 above shall be reduced by such amount. As of the Effective Date, the estimated cost of the ***** package type is between ***** and ***** . b) OPTION #2: ***** MARGIN SHARING Intel will purchase from Marvell a fully packaged, validated and tested Integrated Gb Silicon based on ***** margin sharing whereby Intel and Marvell will split the total available ***** margin dollars based on a pre-determined percentage. It is expected that such ***** margin sharing arrangement will enable the parties to continue to reasonably achieve their respective financial objectives; otherwise, the parties will consider pursuing Marvell's utilization of Intel's fabs as provided in Section 4.2(f) of the Master Agreement. The formula for establishing the purchase price is: IPP = ***** Given: Intel Purchase Price (IPP) - the price Intel pays to Marvell for the Integrated Gb Silicon Compensation Page 2 15 INTEL CONFIDENTIAL Intel ***** ASP (ILA) - the Average Sales Price for an Integrated Gb Silicon sold to external companies for ***** . SEE FURTHER DEFINITION OF ASP BELOW. Marvell ***** Margin Sharing Percentage (M***** MSP) - the percentage of ***** margin dollars Marvell receives from Intel - ***** Marvell Product Cost (MPC) - Marvell's actual cost of the fabricated wafer, wafer sort, testing, less packaging costs Intel ***** Cost (IPC) - Intel's actual cost to ***** the Integrated Gb Silicon Total Part Cost (TPC) - The sum of ***** and ***** Example: If Intel's ***** is $***** , MPC is $***** and ***** is $*****, then ***** is $***** + $***** = $***** and IPP is: IPP = $***** = $***** Intel will pay Marvell $***** per Integrated Gb Silicon and $***** to the packaging house specified in Exhibit D. ii) "Average Sales Price" or "ASP" shall mean Intel's ***** price (which does not include ***** for Integrated Gb Silicon sold to unaffiliated third parties in a bona fide arm's length transaction, assuming such products are generally available for sale to such unaffiliated, bona fide third parties, less only: (i) discounts allowed in amounts customary in the trade for quantity purchases and (ii) amounts allowed or credited on returns. No deductions shall be made for ***** or for cost of ***** . ASP shall be calculated each quarter as: ***** derived from the Integrated Gb Silicon as described above divided by the number of revenue earning units shipped to unaffiliated third parties. 4) QUARTERLY MEETING: Within thirty (30) days after the end of each calendar quarter, or as the parties otherwise mutually agree, the parties shall meet to administer the pricing, commencing one quarter before FCS of the Integrated Gb Silicon. At Intel's option, the parties shall meet in addition on a monthly basis to administer the pricing and make any required Adjustments. a) Quarterly Product Price to Intel: For the purposes of determining the target Intel Product Price above for purposes of Section 3(b) above, prior to the beginning of each calendar quarter, the parties shall meet to set the target Intel Product Price for the upcoming calendar quarter. For the purposes of such calculation, Intel shall use its best efforts to submit a reasonable target ILA and reasonable target IPC and Marvell shall use its best efforts to submit a reasonable target MPC. These targets will then be used to set price for Option #2 for the upcoming quarter. For the purposes of the very first meeting, Marvell will provide the initial MPC based on its expected actual costs from TSMC or Intel approved fab and Marvell and Intel working together shall provide the then current IPC. b) Adjustments to the Product price based on actual ASP/Costs: Within 30 days after the end of each calendar quarter, Intel shall submit its actual ILA of the Integrated Gb Silicon to Marvell and Marvell shall submit its actual Marvell Product Cost to Intel for the actual calendar quarter. Such calculations shall be subject to the audit provision set forth in Section 10 of the main text of the Agreement. Based on each party's submissions, an adjustment to the Intel Product Price will be made in accordance with the ***** margin sharing formula set forth above in 3(b)(i) as set forth in the following formula: Compensation Page 3 16 INTEL CONFIDENTIAL Adjustment = (number of Integrated Gb Silicon units shipped to Intel) * (IPPACTUAL - IPP TARGETED ). If the net of the Adjustments is in Intel's favor, Marvell shall promptly issue a credit memo to Intel, and if the net of the Adjustment is in Marvell's favor, Marvell shall invoice Intel for the net adjustment. In no event shall the adjusted ILA for any quarterly period be less than ***** percent ***** %) of the targeted ILA at the beginning of the quarter. In no event shall the adjusted MPC for any quarterly period be more than ***** percent *****%) of the targeted MPC at the beginning of the quarter. 5) NRE FOR INTEGRATED GB SILICON Intel will pay Marvell for certain NRE costs associated with the development of the Integrated Gb Silicon through ***** . Fees would be paid within 30 days according to the following schedule: TABLE 3
Milestone Payment Completion of Integrated Architecture Spec (I2) $***** & Agreement of Program Schedule (I-8) A0 Tape Out of Integrated Gb Silicon (II-20) $***** Product Samples of Integrated Gb Silicon $*****
In the event of a Termination for Convenience under Section 11 of the Agreement, NRE will be pro-rated on the basis of milestone completions. Notwithstanding the foregoing Table 3, Marvell shall be responsible for all other NRE costs associated with any revisions of the Marvell Gb Phy core. Notwithstanding the foregoing Table 3, Intel shall be responsible for all other NRE costs associated with any revisions of the Intel ***** core. 6) QA CONFORMANCE COSTS FOR THE INTEGRATED GB SILICON Intel will reimburse Marvell for actual and reasonable costs up to $***** associated with QA Conformance and process qualification at TSMC as required in Exhibit F. In the event a new fab is used, Intel will provide similar assistance. Marvell will submit copies of invoices for such expenses and Intel shall remit payment within 45 days. Compensation Page 4 17 EXHIBIT B - PURCHASING TERMS 1. DEFINITIONS A. "Hazardous Materials" are or contain dangerous goods, chemicals, contaminants, substances, pollutants, or any other materials that are defined as hazardous by relevant local, state, national, or international law, regulations, and standards. B. "Item" or "Items" means either the stand-alone Marvell Gb Phy or the Integrated Gb Silicon, or both, as relevant. C. "Purchase Order" is Intel's document setting forth specific line Items ordered and Release information. D. "Release" means Intel's authorization to ship in accordance with the Intel's Purchase Order, and authorizing Marvell to ship a definite quantity of Items to a specified schedule. The Release is contained in the Purchase Order sent to Marvell. 2. TERM OF AGREEMENT A. The term is as set forth in the main text of this Agreement. B. At Intel's option, Items may be scheduled for delivery up to six (6) months following expiration of this Agreement. 3. PRICING A. The pricing for all Items is as set forth in the Compensation Exhibit, Exhibit A to the main text of this Agreement. B. All applicable taxes, including but not limited to sales/use taxes, transaction privilege taxes, gross receipts taxes, and other charges such as duties, customs, tariffs, imposts, and government imposed surcharges shall be stated separately on Marvell's invoice and upon payment by Intel shall be remitted by Marvell to the appropriate tax authority, unless Intel provides sufficient proof of tax exemption. In the event that Intel is prohibited by law from making payments to Marvell unless Intel deducts or withholds taxes therefrom and remits such taxes to the local taxing jurisdiction, then Intel shall duly withhold and remit such taxes and shall pay to Marvell the remaining net amount after the taxes have been withheld. Intel shall not reimburse Marvell for the amount of such taxes withheld. When property is delivered and/or services are provided or the benefit of services occurs within jurisdictions in which Marvell collection and remittance of taxes is required by law, Marvell shall have sole responsibility for payment of said taxes to the appropriate tax authorities. In the event Marvell does not collect tax from Intel, and is subsequently audited by any tax authority, liability of Intel will be limited to the tax assessment, with no reimbursement for penalty or interest charges unless such failure to pay is based on Intel's claim of tax exemption or other information provided by Intel. Each party is responsible for its own respective income taxes or taxes based upon gross revenues, including but not limited to business and occupation taxes. 4. INVOICING AND PAYMENT A. Payment is made when Intel's check is mailed or EDI funds transfer initiated. Intel shall make payment within ***** days after Intel's receipt of the Items. B. Original invoices or packing lists shall be submitted and shall include: purchase agreement number from the Purchase Order, purchase order number, line Item number, Release number, part number, complete bill to address, description of Items, quantities, unit price, extended totals, and any applicable taxes or other charges. All costs forwarded to Intel for reimbursement of expenses agreed under the terms of this Agreement shall be net of any reclaimable Value Added Taxes ("VAT") incurred on such expenses. Intel's payment shall not constitute acceptance. C. Marvell agrees to invoice Intel no later than ***** days after shipment of Items. Intel will not be obligated to make payment against any invoices submitted after such period. Purchasing Terms Page 1 18 INTEL CONFIDENTIAL 5. FORCE MAJEURE Neither party shall be held liable for failure to fulfill its obligations other than payment obligations under this Agreement, if the failure is caused by flood, extreme weather, or other acts of God or natural calamity, fire, theft, war, riot, embargo, earthquake, acts of governmental agency or military authority, or similar causes beyond the control of such party, and the term for performance shall be increased to a reasonable period of time. If delivery is to be delayed by such contingencies, Marvell shall immediately notify Intel in writing and Intel may either (i) extend time of performance; or (ii) terminate all or part of the uncompleted portion of the Purchase Order at no cost to Intel, except for the Integrated Gb Silicon. 6. DELIVERY, RELEASES SCHEDULING AND ALLOCATION The management of existing accepted Releases for the stand-alone Marvell Gb Phy will, to the extent commercially reasonable, occur in accordance with the following table 1: TABLE 1
Days prior to Upside delivery <30 ***** % 30 - 89 ***** % 90+ ***** %
The parties agree that any charges incurred in this Section 6 will be invoiced and paid in accordance with this Exhibit B. A. Rescheduling and Cancellation of the Stand-Alone Marvell Gb Phy. Intel may reschedule and cancel any Releases for the stand-alone Marvell Gb Phy strictly in accordance with the following table 2: TABLE 2
CANCELLATION CHARGE AS DAYS BEFORE SCHEDULED A PERCENTAGE OF THE DELIVERY DATE RESCHEDULING RULE CANCELLATION RULE UNIT PURCHASE PRICE --------------------- ----------------- ----------------- ---------------------- ***** No rescheduling No cancellation N/A permitted. permitted. ***** At any time between No cancellation N/A ***** and ***** days; permitted. Marvell must receive notice of such request prior to Marvell's consignment of any Items to a carrier; ONLY ***** permitted, in whole or in part, at no additional charge to Intel; delivery to be rescheduled must be rescheduled for delivery no later than ***** days after the originally scheduled delivery date. ***** At any time after ***** charge to Intel, ***** % ***** days; Marvell provided that Marvell must receive notice of receives notice of such such request prior to cancellation on or Marvell's consignment greater than ***** of any Items to a calendar days prior to carrier; only ***** Marvell's consignment permitted, in whole or of any Items to a in part, at ***** carrier. additional charge to Intel; delivery to be rescheduled must be rescheduled for delivery no later than ***** days after the originally scheduled delivery date.
Purchasing Terms Page 2 19 INTEL CONFIDENTIAL B. Rescheduling and Cancellation of Integrated Gb Silicon. Intel may reschedule and cancel any Releases for the Integrated Gb Silicon strictly in accordance with the following table 3:: TABLE 3
CANCELLATION CHARGE AS DAYS BEFORE SCHEDULED A PERCENTAGE OF THE DELIVERY DATE RESCHEDULING RULE CANCELLATION RULE UNIT PURCHASE PRICE --------------------- ----------------- ----------------- ---------------------- ***** No rescheduling No cancellation N/A permitted. permitted. ***** At any time between No cancellation N/A ***** and ***** days; permitted. Marvell must receive notice of such request prior to Marvell's consignment of any Items to a carrier; ONLY ***** permitted, in whole or in part, at ***** additional charge to Intel; delivery to be rescheduled must be rescheduled for delivery no later than ***** days after the originally scheduled delivery date. ***** At any time after ***** receives notice In accordance with ***** days; Marvell of such cancellation on Table 4 of this Exhibit must receive notice of or greater than ***** B. such request prior to calendar days prior to Marvell's consignment Marvell's consignment of any Items to a of any Items to a carrier; only ***** carrier. permitted, in whole or in part, at ***** additional charge to Intel; delivery to be rescheduled must be rescheduled for delivery no later than ***** days after the originally scheduled delivery date.
Purchasing Terms Page 3 20 INTEL CONFIDENTIAL TABLE 4
Days BEFORE SCHEDULED DELIVERY DATE CANCELLATION CHARGE AS A PERCENTAGE OF THE UNIT PURCHASE PRICE ------------------------------------ -------------------------------- ***** ***** ***** ***** ***** ***** ***** *****
* In the event TSMC or other approved fab imposes a penalty on Marvell for cancellation of reserved capacity beyond ***** days, the parties agree to renegotiate the cancellation charge applicable at ***** days. C. Intel shall provide Marvell with a 6-month rolling forecast monthly for Items. D. Lead-time for Items shall be 90 days. E. If for any reason Marvell discontinues the manufacture of any Item during the term of this Agreement or within one (1) year after the final delivery under this Agreement, Marvell shall give Intel at least ***** days prior written notice of such Item discontinuance, during which time Intel shall have the option to place a final Release for such Items for delivery to Intel within an agreed upon period. If any warranty return claims are made for such discontinued Items, then such returns will be subject to the warranty provisions in Section 7. F. In the event Marvell is on ***** with TSMC or another approved fab, Marvell will use ***** efforts to ***** with TSMC or such other approved fab. Marvell agrees to advise Intel of the development of ***** as soon as reasonably practical, and parties will discuss in good faith Intel's participation in trying to help secure such Items on order for Intel. If Intel has ***** at TSMC or a mutually agreed to fab, for other Intel products, the parties will discuss in good faith the possibility of ***** to produce the Items solely as necessary to supply Intel with any quantities necessary to alleviate a ***** ; provided, however, that neither party shall have any liability to the other party for any failure to *****. G. Notwithstanding anything else in this Agreement, failure to meet the delivery date(s) that comply with the terms of this Agreement in the Purchase Order for the stand-alone Marvell Gb Phy other than for force majeure, within five (5) days after such scheduled delivery date(s), shall be considered a material breach of contract and shall allow Intel to terminate the order for the Marvell Gb Phy and/or any subsequent Releases in the Purchase Order without any liability. 7 ACCEPTANCE AND WARRANTY A. Intel may inspect and test all Items at reasonable times before, during, and after manufacture. If any inspection or test is made on Marvell's premises, Marvell shall provide reasonable facilities and assistance for the safety and convenience of Intel's inspectors in such manner as shall not unreasonably hinder or delay Marvell's performance. All Items shall be received subject to Intel's inspection, testing, approval, and acceptance at Intel's premises notwithstanding any inspection or testing at Marvell's premises or any prior payment for such Items. Items rejected by Intel as not conforming to this Agreement or Item specifications, whether provided by Intel or furnished with the Item shall be subject to Marvell's RMA procedures. B. Except as noted in this Section B, the warranty obligations of Intel and Marvell are as set forth in Section 6 of the main text of the Agreement, which such obligations the parties agree shall survive any delivery, inspection, acceptance, payment, or resale of the Items. Notwithstanding the foregoing, Marvell makes the following additional warranties: (i) The Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon do not infringe any third party's intellectual property rights; (ii) Marvell has the necessary right, title, and interest in and to the Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon to provide the Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon to Intel, and the Purchasing Terms Page 4 21 INTEL CONFIDENTIAL Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon will be free of liens and encumbrances; (iii) The Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon are new, and of the grade and quality specified in Exhibit D; (iv) The Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon are free from defects in workmanship and material, conform to all samples, drawings, descriptions, and specifications furnished or published by Marvell, and conform to any other agreed-to specifications; and, (v) The Marvell Gb Phy and the Integrated Gigabit Phy as embodied in the Integrated Gb Silicon conform to the manufacturing quality provisions set forth in Exhibit E; Any software (including firmware) provided with, embedded in, or necessary to operate the Item being purchased by Intel ("Software") will function without error or interruption related to Date Data from more than one century; all Date Data (whether received from users, systems, applications or other sources) include an indication of century in each instance; and all date output and results, in any form, shall include an indication of century in each instance. As used herein, "Date Data" means any data or input, whether generated within the Item or communicated to it, which includes an indication of or reference to date. In the event of any breach of the warranties set forth in (i) and (ii) of this Section 7 B., Intel's sole remedy shall be the indemnification right in Section 11 A. and B. of this Exhibit B. Intel also makes the following additional warranties: (vi) The Intel ***** and the Integrated Intel ***** as embodied in the Integrated Gb Silicon sold to Intel do not infringe any third party's intellectual property rights; and, (vii) Intel has the necessary right, title, and interest to in and to the Intel ***** and the Integrated Intel ***** as embodied in the Integrated Gb Silicon to provide the Intel ***** to Marvell, and the Intel ***** is free of liens and encumbrances In the event of any breach of the warranties set forth in (vi) and (vii) of this Section 7 B., Marvell's sole remedy shall be the indemnification right in Section 11 C. and D. of this Exhibit B. C. If Marvell breaches any of the foregoing warranties, or Items are otherwise defective or non-conforming, during a period of ninety (90) days after Intel's acceptance of Items, which such acceptance for purposes of this Section 7 C. shall be deemed to occur on the earlier of the actual date of such acceptance or thirty (30) days after delivery of the Items by Marvell to Intel, Marvell shall, at its option, promptly repair, replace, or refund the amount paid for such Items. Marvell shall bear the cost of shipping and risk of loss of all defective or non-conforming Items while in transit, provided that Marvell's examination of such Items discloses to Marvell's satisfaction that such Items are defective and such defects are not caused by accident, abuse, misuse, neglect, alteration, improper installation, repair or alteration by someone other than Marvell. D. THE WARRANTIES BY MARVELL AND INTEL SET FORTH HEREIN ARE EXCLUSIVE, AND IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, WHICH ARE HEREBY EXPRESSLY DISCLAIMED. 8 PRODUCT SPECIFICATIONS/ IDENTIFICATION/ERRATA A. Marvell shall not modify the specifications for Integrated Gb Silicon without Intel's written consent. Marvell shall notify Intel in advance of any material changes in the manufacturing process, product, and packing material or test program of the Integrated Gb Silicon as follows: (a) ***** days advanced notice for changes requiring customer qualification or notification; and, (b) ***** days advanced notice for changes that do not require customer approval. Purchasing Terms Page 5 22 INTEL CONFIDENTIAL B. Marvell shall promptly notify Intel of any modifications of the specifications for the Marvell Gb Phy. Additionally, Marvell shall notify Intel in advance of any material changes in the manufacturing process, product, and packing material or test program of the Marvell Gb Phy as follows: (a) ***** days advanced notice for changes requiring customer qualification or notification; and, (b) ***** days advanced notice for changes that do not require customer approval. C. Marvell shall cooperate with Intel to provide configuration control and traceability systems for Items supplied hereunder. D. Marvell shall provide Intel with an errata list for each Item and shall promptly notify Intel in writing of any new errata with respect to the Items. E. Marvell shall provide additional errata reporting as specified in Exhibit F Support. F. In addition to remedies provided above, Marvell shall be responsible for Rework costs arising out of any breach of warranty provided for in Section 7 of this Exhibit B. In addition to the remedies also provided above, Intel shall be responsible for Rework costs arising out of any breach of warranty provided for in Section 7 of this Exhibit B. For purposes of this Exhibit B, the term "Rework" means the process of (i) diagnosing, retrieving, and accessing a non-conforming or defective Item; (ii) repairing such Item so that is is conforming and free of defects and/or replacing such Item with an Item which is conforming and free from defects, (iii) if necessary, reconfiguring an Intel or a Marvell product to accommodate the repaired or replaced Item or the covered Item, (iv) testing the repaired or replaced Item to ensure that the repaired or replaced Item is conforming and free from defects; and (v) returning the Item which is conforming and free from defects to the location where the con-conforming or defective Item was at the time the non-conformance or defect was discovered. For purposes of this Section 8 F. only, "Item" or "Items" shall also be defined to include the Intel ***** and the Integrated Intel ***** as embodied in the Integrated Gb Silicon, as applicable. 9 PACKING AND SHIPMENT/PASSAGE OF TITLE All items shall be delivered Free Carrier ("FCA", Incoterms 2000) from Marvell's facility in Taiwan, or otherwise as specified in the Release. In any event, title and risk of loss shall pass to Intel at this point outside the U.S.. All Items shall be prepared for shipment in a manner which: (i) follows good commercial practice; (ii) is acceptable to common carriers for shipment at the lowest rate; and (iii) is adequate to ensure safe arrival. Marvell shall mark all containers with necessary lifting, handling and shipping information, purchase order number, date of shipment, and the names of the Intel and Marvell. Intel shall notify Marvell of the method of shipment and expected delivery date. If no instructions are given, Marvell shall select the most cost effective carrier, given the time constraints known to Marvell. Marvell shall ship only the quantity of Items specified in the Release. Intel may return at Marvell's expense any Items in excess of the quantity stated in the Release. 10 OWNERSHIP SEE SECTION 4 OF THE MAIN TEXT OF THE AGREEMENT FOR CONTROLLING TERMS. 11 INTELLECTUAL PROPERTY INDEMNIFICATION A. Marvell Obligation. Marvell will defend or settle any suit or proceeding brought against Intel based upon a claim that Intel's use or distribution of the Marvell Gb Phy and the Marvell Gigabit Phy as embodied in the Integrated Gb Silicon infringes or misappropriates the Intellectual Property Rights of a third party, and Marvell will pay the damages and costs finally awarded against Intel up to such limits, so long as: (i) Marvell is notified promptly in writing of such suit or proceeding, (ii) Marvell controls the defense and settlement of the suit or proceeding, and (iii) Intel cooperates reasonably, and gives all necessary authority, information and assistance to Marvell (at Marvell's expense) to defend and settle the suit or proceeding. Notwithstanding the foregoing, Marvell is not obligated to defend or settle any such suit or proceeding and is not obligated to pay any such damages or costs, if such suit or proceeding arises out of either: (A) a combination of the Marvell Gb Phy or the Marvell Gigabit Phy as embodied in the Integrated Gb Silicon with devices or programs not supplied Purchasing Terms Page 6 23 INTEL CONFIDENTIAL by Marvell, except where such has no noninfringing use other than in such combination; or, (B) a modification, alteration or amendment of the Marvell Gb Phy and the Marvell Gigabit Phy as embodied in the Integrated Gb Silicon. B. Limitations on Marvell Obligation. Marvell shall not be responsible for any costs, expenses or compromise incurred or made by Intel without Marvell's prior written consent. If a suit or other proceeding has been filed, or it reasonably appears that one will be filed or that an injunction shall issue, Marvell may, in its sole discretion and at its own expense, procure for Intel the right to continue using the Marvell Gb Phy and the Marvell Gigabit Phy as embodied in the Integrated Gb Silicon, replace it with a non-infringing technology or modify it so that it becomes non-infringing, provided that the infringement would not have occurred but for such use or combination. C. Intel Obligation. Intel will defend or settle any suit or proceeding brought against Marvell based upon a claim that Intel's use or distribution of the Intel ***** as embodied in the Integrated Gb Silicon infringes or misappropriates the Intellectual Property Rights of a third party, and Intel will pay the damages and costs finally awarded against Marvell up to such limits, so long as: (i) Intel is notified promptly in writing of such suit or proceeding, (ii) Intel controls the defense and settlement of the suit or proceeding, and (iii) Marvell cooperates reasonably, and gives all necessary authority, information and assistance to Intel (at Intel's expense) to defend and settle the suit or proceeding. Notwithstanding the foregoing, Intel is not obligated to defend or settle any such suit or proceeding and is not obligated to pay any such damages or costs, if such suit or proceeding arises out of either: (A) a combination of the Intel ***** as embodied in the Integrated Gb Silicon with devices or programs not supplied by Intel, except where such has no noninfringing use other than in such combination; or, (B) a modification, alteration or amendment of the Intel ***** as embodied in the Integrated Gb Silicon. D. Limitations on Intel Obligation. Intel shall not be responsible for any costs, expenses or compromise incurred or made by Marvell without Intel's prior written consent. If a suit or other proceeding has been filed, or it reasonably appears that one will be filed or that an injunction shall issue, Intel may, in its sole discretion and at its own expense, procure for Marvell the right to continue using the Intel ***** as embodied in the Integrated Gb Silicon, replace it with a non-infringing technology or modify it so that it becomes non-infringing, provided that the infringement would not have occurred but for such use or combination. 12 HAZARDOUS MATERIALS A. If Items or any services provided hereunder include Hazardous Materials, Marvell represents and warrants that Marvell and its personnel providing services to Intel understand the nature of and hazards associated with the design and/or service of Items including handling, transportation, and use of such Hazardous Materials, as applicable to Marvell. Prior to causing Hazardous Materials to be on Intel's property, Marvell shall obtain written approval from Intel's Site Environmental/Health/Safety organization. Marvell will be responsible for and indemnify Intel from any liability resulting from the actions of Marvell or its contractors in connection with: (i) providing such Hazardous Materials to Intel; and/or (ii) the use of such Hazardous Materials in providing services to Intel. B. Marvell will timely provide Intel with material safety data sheets and any other documentation reasonably necessary to enable Intel to comply with applicable laws and regulations. C. Marvell hereby certifies to the best of its knowledge that Items supplied to Intel do not contain and are not manufactured with any ozone depleting substances, as those terms are defined by law. 13 CUSTOMS CLEARANCE Upon Intel's request, Marvell will promptly provide Intel with a statement of origin for all Items and with applicable customs documentation for Items wholly or partially manufactured outside of the country of import. 14 COMPLIANCE WITH LAWS A. Marvell shall comply with all national, state, and local laws and regulations governing the manufacture, transportation, and/or sale of Items and/or the performance of services in the course of this Agreement. In the United States, these may include, but are not limited to, Department of Commerce, Environmental Protection Agency, and Department of Transportation regulations applicable to Hazardous Materials. Purchasing Terms Page 7 24 INTEL CONFIDENTIAL B. Marvell represents and agrees that it is in compliance with Executive Order 11246 and implementing Equal Employment Opportunity regulations and the Immigration Act of 1987, unless exempted or inapplicable. 15 SPECIFIC PERFORMANCE Notwithstanding anything else contained in this Agreement, the parties hereto agree that failure to perform certain obligations undertaken in connection with this Agreement would cause irreparable damage, and that monetary damages would not provide an adequate remedy in such event. The parties further agree that failure to deliver against accepted Purchase Orders, or to deliver confirmed supply or pricing, are such obligations. Accordingly, it is agreed that, in addition to any other remedy to which the non breaching party may be entitled, at law or in equity, the non breaching party shall be entitled to injunctive relief to prevent breaches of the provisions of this Agreement, and an order of specific performance to compel performance of such obligations in any action instituted in any court of the United States or any state thereof having subject matter jurisdiction. 16 SURVIVAL The provisions of Sections 4, 6, 7, 9 and 11 will survive any termination or expiration of this Agreement. 17 CONTROLLING TERMS Notwithstanding anything to the contrary set forth in this Exhibit B, in the event of a conflict between the terms of this Exhibit B and the terms of the main text of the Agreement, the terms of the main text of the Agreement shall control and supercede any conflicting provisions set forth in this Exhibit B. Purchasing Terms Page 8 25 EXHIBIT D STATEMENT OF WORK FOR ***** - -------------------------------------------------------------------------------- 1.0 PURPOSE The purpose of this SOW is to set forth the terms and conditions under which Marvell and Intel shall develop an Intel product currently known as "*****". The parties must agree to any material changes to ***** that is encompassed in this SOW in writing. 2.0 DEFINITIONS PHY Physical Layer Device. The device/block that implements the AFE. ***** ***** The name of the logic that implements the ***** standard. G***** Gigabit ***** AFE Analog Front End... converts digital signals to analog for input and output on physical interface LVS Layout Verification Service SDF Standard Delay Format. IBIS An industry standard simulation / signal characterization model of IOs. EEPROM Electrically Erasable Programmable Read Only Memory. VCS Synopsys's HDL simulator product. Modelsim Model Technology's HDL simulator product. DB The library format of Synopsys sythesis libraries. Synopsys Synthesis tool company. www.synopsys.com Verilog An industry standard HDL language HDL Hardware Design Language. DFT Design For Test. IO Input/Output. Typically refers to a silicon pin/pad. RAM Random Access Memory. DMA Direct Memory Access. DRC Design Rule Check. DSP Digital Signal Processor. ***** *****. This is the type of bus protocol implemented by *****. ***** Controller The logic that provides the ***** function along with DMA and a host interface (e.g. PCI). IAS Integration Architecture Specification - is the overall system specification for ***** and will be the reference point for all functions and features
STATEMENT OF WORK FOR ***** Page 1 26 INTEL CONFIDENTIAL MII Media Independent Interface GPIO General Purpose Input/Output. This is a software controllable input/output pin/pad. GMII Gigabit Media Independent Interface TBI Ten Bit Interface ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ***** ACPI Advanced Configuration and Power Interface: A specification developed by Intel, Microsoft, and Toshiba for describing and enabling power management functionality provided by a computer system ***** ***** ASF Alerting Standards Form CIM Common Information Model: DMTF standard for management data schema DAC Dual Address Cycle IAS Integrated Architecture Specification: Document of design requirements for integrating the ***** and PHY. ***** ***** MCM Multi-Chip Module MOF Management Object Format: A format for storing management data. PXE Pre-boot eXecution Environment. UTP Unshielded Twisted Pair. WBEM Web Based Enterprise Management: Initiative for management proposed by six companies including Intel and Microsoft through the DMTF. ***** ***** ***** ******: An IBM trademarked term, used in place of *****, that describes the capability of remotely bringing a ***** from a low to a high power state. ***** ***** ***** ***** ER Engineering Release (Product is placed under ECO Control) PLC Product Life Cycle MRD Market Requirements Document PRD Product Requirements Document SSD Systems Specification Document
STATEMENT OF WORK FOR ***** Page 2 27 INTEL CONFIDENTIAL NQL Network Quality Labs...Intel quality assurance (QA) process for hardware and software SKU Stock Keeping Unit PDT Intel and Marvell's Joint Program Development Team. A0 A0 is used to indicate the first revision of the silicon. If the next revision only changes metal layer, the number increments (e.g. A1). If all (or most) layers change, the letter increments and the number resets to zero (e.g. B0).
3.0 PROGRAM MANAGEMENT The parties agree to each assign dedicated Program Managers and Engineering Project Managers to this project. The Intel Program Manager will have overall project responsibility.
PROGRAM AND ENGINEERING PROJECT MANAGERS ================================================================================================================== COMPANY NAME TITLE PHONE NUMBER EMAIL ADDRESS ================================================================================================================== Intel ***** Program Manager ***** ***** Intel ***** Engineering Manager ***** ***** Marvell ***** Account Program Manager ***** ***** Marvell ***** VP Product Development, ***** ***** Datacom ==================================================================================================================
In addition, when applicable, both parties agree to assign cross-functional team members to the project. These members may not be dedicated to the project, but do include representation from at least the following functions or disciplines: - - Marketing - - Digital Engineering (ASIC and CMOS micro-architecture) - - Analog Engineering (IO cells, PHY, and noise analysis) - - CAD Engineering (Layout, DRC) - - Board Engineering - - Foundry Support - - Manufacturing Test Engineering - - Quality & Reliability Engineering - - Product Engineering - - Packaging Engineering - - Customer Support - - Applications Engineering - - Operations - - Silicon Validation - - Firmware / Software Engineering 4.0 PRODUCT REQUIREMENTS AND SPECIFICATIONS The following documents describe the ***** product requirements and are incorporated herein. - - ***** Product Requirements are attached as Attachment #1 to this Project Statement) - - ***** Integration Architecture Specification (IAS) as referenced in "Phase I" of the Statement of Work. This document will be attached as Attachment #2 to this Project Statement after completion of Phase I. STATEMENT OF WORK FOR ***** Page 3 28 INTEL CONFIDENTIAL 5.0 STATEMENT OF WORK ("SOW") - PROJECT DELIVERABLES AND SCHEDULE; RESTRICTION ON USE AND DISCLOSURE OF PARTIES' INTELLECTUAL PROPERTY The SOW in Attachment #3 is incorporated in this Project Statement. The SOW details the Deliverables and associated milestone dates for this project. The acceptance criteria are identified in Attachment #4. In addition to the protections on each parties Intellectual Property Rights set forth in the main text of the Agreement, each party agrees not to violate the other party's Intellectual Property Rights in connection with the performance of its obligations under this SOW and the attachments hereto. The parties agree that such violations would include but not be limited to, de-compiling any software code or reverse engineering any Item (as defined in Exhibit B to the main Agreement) or model delivered to the other in accordance with the main text of the Agreement or any exhibit thereto, including this SOW and the attachments hereto. INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: By: ----------------------------- ----------------------------- Printed Name: Printed Name: ------------------- ------------------- Title: Title: -------------------------- -------------------------- Date: Date: --------------------------- --------------------------- STATEMENT OF WORK FOR ***** Page 4 29 INTEL CONFIDENTIAL ATTACHMENT #1 TO PROJECT STATEMENT #1 ***** PRODUCT REQUIREMENTS REVISION 0.80 REQUIRED FEATURES: 1. Single Integrated *****/PHY component. 2. ***** Mbps operation on ***** 3. ***** operation on ***** 4. Compliant with ***** 5. Supports Autonegotiation of ***** 6. IEEE performance consistent with ***** 7. ***** Duplex ***** Duplex support. 8. ***** compliant, supporting ***** modes; ***** bit,***** bit modes. 9. ***** compliant, supporting ***** modes; ***** bit, ***** bit modes. 10. Power supplies: a. I/O Supply ***** b. Analog Supply ***** c. Digital Supply ***** d. Digital Supply ***** e. Analog Supply ***** 11. *****tolerant inputs for ***** buffers. 12. ***** power consumption: **********W a. ***** CORE: < ***** w b. phy core: *****w c. *****misc io: *****w d. phy io: *****w 13. temperature range ***** operation ***** max (theta)ja = ***** 14. package: ***** however, the current cost estimates set forth in table 2 of exhibit a are based on the assumption that the package type will be the same cost of a typical ***** 15. external microwire eeprom interface ***** 16. external flash interface ***** 17. differential pair interfaces ***** 18. tbi fiber phy interface ***** 19. power management ***** compliant. 20. software controllable gpio drivers/inputs ***** 21. led outputs for ***** ***** 1. sleep wake-up mode *****: < *****w 2. sleep power-down mode *****<*****mw statement of work for ***** page 5 30 INTEL CONFIDENTIAL INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: By: ----------------------------- ----------------------------- Printed Name: Printed Name: ------------------- ------------------- Title: Title: -------------------------- -------------------------- Date: Date: --------------------------- --------------------------- STATEMENT OF WORK FOR ***** Page 6 31 INTEL CONFIDENTIAL ATTACHMENT #2 TO PROJECT STATEMENT #1 INTEGRATION ARCHITECTURE SPECIFICATION REVISION 0.11 (TO BE COMPLETED AT THE END OF PHASE I) The purpose of this section is to provide a framework for the Integration Architecture Specification ("IAS"). The final IAS may incorporate additional items. *****/PHY INTERFACE Connections Timing Requirements Functional Requirements of Signals Interface Reset Methodology Interface Clock Requirements Initialization Sequence Power Down Sequence IO CELLS Cell List/Summary Electrical Requirements - Internal, External, Timing ***** RAM CELLS ***** CLOCK/RESET REQUIREMENTS ***** TEST INTERFACE ***** PHY Standalone DFT Interface Timing Requirements of DFT Interface FULL CHIP PIN LIST Pin List for each Interface List of shared/overloaded pins PACKAGE Package Type and Mechanicals Package Electrical and Thermal Characteristics Power / Ground Requirements ***** STATEMENT OF WORK FOR ***** Page 7 32 INTEL CONFIDENTIAL INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: By: ----------------------------- ----------------------------- Printed Name: Printed Name: ------------------- ------------------- Title: Title: -------------------------- -------------------------- Date: Date: --------------------------- --------------------------- STATEMENT OF WORK FOR ***** Page 8 33 INTEL CONFIDENTIAL ATTACHMENT #3 TO PROJECT STATEMENT #1 ***** STATEMENT OF WORK REVISION 0.7 PHASE I: *****
TARGET TARGET START END BY/ MS DATE DATE ACTIVITY/DELIVERABLE BETWEEN TO -- ------ ------ -------------------- ------- -- I-1 ***** ***** ***** Intel/ Marvell I-2 ***** ***** ***** Intel/ Marvell I-3 ***** ***** Intel Marvell I-4 ***** ***** Marvell Intel I-5 ***** ***** Intel Marvell I-6 ***** ***** Intel Marvell I-7 ***** ***** ***** Intel/ Marvell I-8 ***** ***** ***** Intel/ Marvell I-9 ***** ***** ***** Intel/ Marvell I-10 ***** *****
STATEMENT OF WORK FOR ***** Page 9 34 INTEL CONFIDENTIAL PHASE II: *****
TARGET START TARGET END MS DATE DATE ACTIVITY/DELIVERABLE BY/ BETWEEN TO - ------ ------ ---------- -------------------- -------------- ------ II-1 [ ] ***** ***** Marvell Intel II-2 [ ] ***** ***** Marvell Intel II-2a [ ] ***** ***** Marvell Intel II-3 [ ] ***** ***** Marvell Intel II-3a ***** ***** ***** Intel / Marvell II-4 [ ] ***** ***** Marvell Intel II-5 [ ] ***** ***** Intel Marvell II-6 [ ] ***** ***** Intel Marvell II-7 [ ] ***** ***** Marvell Intel II-7a [ ] ***** ***** Intel Marvell II-7b ***** ***** ***** Intel / Marvell II-7c [ ] ***** ***** Marvell Intel II-7d ***** ***** ***** Marvell II-8 [ ] ***** ***** Intel Marvell II-9 [ ] ***** ***** Intel/ Marvell II-10 [ ] ***** ***** Marvell Intel II-11 [ ] ***** ***** Marvell II-12 [ ] ***** ***** Marvell Intel II-13 [ ] ***** ***** Intel II-14 [ ] ***** ***** Marvell II-15 [ ] ***** ***** Intel/ Marvell II-16 [ ] ***** ***** Marvell Intel
STATEMENT OF WORK FOR ***** Page 10 35 INTEL CONFIDENTIAL II-17 ***** ***** Intel Marvell II-18 ***** ***** Marvell II-18a ***** ***** Intel/ Marvell II-19 ***** ***** Intel/ Marvell II-20 ***** ***** Marvell
PHASE III: *****
TARGET START TARGET END MS DATE DATE ACTIVITY/DELIVERABLE BY/ BETWEEN TO - ------ ------ ---------- -------------------- -------------- ------ III-1 ***** ***** ***** Intel/ Marvell III-2 ***** ***** Intel Marvell III-3 ***** ***** Marvell Intel III-4 ***** ***** ***** Intel/ Marvell III-5 ***** ***** ***** Intel/ Marvell III-6 ***** ***** Intel/ Marvell Intel III-7 ***** ***** ***** Intel/ Marvell III-8 FCS of Integrated Gb Silicon Intel
INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: By: ----------------------------- ----------------------------- Printed Name: Printed Name: ------------------- ------------------- Title: Title: -------------------------- -------------------------- Date: Date: --------------------------- --------------------------- STATEMENT OF WORK FOR ***** Page 11 36 INTEL CONFIDENTIAL ATTACHMENT #4 TO PROJECT STATEMENT #1 INTEL'S ***** ACCEPTANCE CRITERIA REVISION 0.7 This acceptance criteria document attempts to provide more detail on what constitutes an acceptable deliverable to Intel or acceptable joint action between Marvell and Intel. Refer to the Statement of Work (Attachment #3) for the deliverable or joint action. The acceptance criteria for each Intel deliverable/joint action is shown here: PHASE I
CORRESPONDING SOW MS ACTIVITY/DELIVERABLE - ------------- -------------------- I-1 ***** I-2 ***** I-4 ***** I-7 ***** I-8 ***** I-9 ***** I-10 *****
PHASE II
CORRESPONDING SOW MS ACTIVITY/DELIVERABLE - ------------- -------------------- II-1 ***** II-2 ***** II-2a ***** II-3 ***** II-3a ***** II-4 ***** II-7 ***** II-7b ***** II-7c ***** II-9 ***** II-10 ***** II-12 ***** II-15 ***** II-16 *****
STATEMENT OF WORK FOR ***** Page 12 37 INTEL CONFIDENTIAL II-18a ***** II-19 *****
PHASE III
CORRESPONDING SOW MS ACTIVITY/DELIVERABLE - -------------- -------------------- III-1 ***** III-3 ***** III-4 ***** III-5 ***** III-6 ***** III-7 ***** III-8 FCS of Integrated Gb Silicon
INTEL CORPORATION MARVELL SEMICONDUCTOR, INC. By: By: ----------------------------- ----------------------------- Printed Name: Printed Name: ------------------- ------------------- Title: Title: -------------------------- -------------------------- Date: Date: --------------------------- --------------------------- STATEMENT OF WORK FOR ***** Page 13 38 INTEL CONFIDENTIAL EXHIBIT E QUALITY ASSURANCE REQUIREMENTS 1.0 PURPOSE This document outlines Intel's minimum expectations for the quality and reliability requirements for the Marvell Gb Phy product and the Integrated Gb Silicon. 1.1 MARVELL GB PHY The Marvell Gigabit Phy should meet all the criteria listed in the Intel specification ***** Rev 4 - General Procurement Specification for Silicon Integrated circuits. Intel must approve any exceptions to the spec. Any branding requirements from Intel's ***** spec must be explicitly called out in Exhibit E. Any requirements in `Appendix D' of ***** will be superceded by requirements listed in Exhibit E. 1.1A INTEGRATED GB SILICON The Integrated Gb Silicon part should meet all the criteria listed in the Intel specification ***** Rev 4 - General Procurement Specification for Silicon Integrated circuits with the outgoing DPM specified below (< *****dpm). intel must approve any exceptions to the spec. any branding requirements from intel's ***** spec must be explicitly called out in exhibit e. any requirements in `appendix d' of ***** will be superceded by requirements listed in exhibit e. 1.2 retention of records marvell will maintain records pertaining to the manufacture and inspection of all items for 1 year. this should include but is not limited to: a) documentation b) reported data c) tests performed d) inspections e) process changes 1.3. right to audit intel reserves the right to conduct an on-site audit of marvell's supplier's processes with reasonable advance notice. the audit may cover basic quality operating systems, manufacturing, test, etc. marvell will facilitate this meeting between the two organizations. 1.4. qualification process (for marvell gb phy and integrated gb silicon) marvell will provide, upon reasonable request, any documentation reasonably required to assist intel in determining the baseline quality level for the item. requested documentation will include, but is not limited to: a) qualification plan and report b) test plan and report c) certification reports for fab process and standard package assembly process. intel may re-qualify the package assembly process at its own expense if it chooses. the intent is to establish an understanding of quality levels and correlate marvell's qualification activities to intel's. when engineering/design changes occur, intel may require marvell to resubmit certain documentation as it pertains to scheduled item changes and updates. quality assurance requirements page 1 39 INTEL CONFIDENTIAL 1.5. SAMPLE SIZES AND ACCEPT CRITERIA FOR RELIABILITY STRESSES
Units Number per Stress/test Risk of lots lot PTQ PDQ FLQ Notes ----------- ----- ------- ----- ----- ----- ----- ----- 3-Temperature Quality Validation ***** ***** ***** ***** ***** ***** ***** Test Fault Coverage ***** ***** ***** ***** ***** ***** ***** Infant Mortality Evaluation ***** ***** ***** ***** ***** ***** ***** Lifetest ***** ***** ***** ***** ***** ***** ***** Preconditioning ***** ***** ***** ***** ***** ***** ***** Temperature Cycle Condition "C" ***** ***** ***** ***** ***** ***** ***** HAST, 85/85 ***** ***** ***** ***** ***** ***** ***** ESD HBM ***** ***** ***** ***** ***** ***** ***** ESD CDM ***** ***** ***** ***** ***** ***** ***** Latchup I/O ***** ***** ***** ***** ***** ***** ***** Latch-up Vcc ***** ***** ***** ***** ***** ***** *****
NOTES: 1) Quality Validation DPM requirement is ***** DPM for the Integrated product and ***** DPM for the stand-alone Marvell Gb Phy. Outgoing production DPM will meet or exceed the ***** DPM IME upper limit in accordance with the "Quality Improvement and Corrective Actions" requirements listed in Exhibit E. 2) At least ***** SCAN coverage on all digital blocks except where prevented by DSP or other performance issues. At least ***** toggle coverage on non-SCAN digital blocks. At least ***** functional coverage on analog blocks. In cases where it is difficult to determine precise fault coverage percentage, Intel and Marvell will need to agree that the intent of the fault coverage goal has been met. 3) IME units should be the same units that have been run through***** 4) Readouts for IME and Lifetest to be performed at ***** hours. 5) Lifetest units should be a subset of the IME/QV units. 6) Preconditioning will be minimum *****. Weight step is optional in preconditioning flow. 7) ***** hours of 85/85 may be substituted for ***** hours HAST. 8) CDM ESD will be performed to JEDEC std., and will be required only for the Integrated product. 9) For the stand-alone (PQFP) Gigabit product, the Latchup temperature will be reduced to *****C due to socketing issues. 1.6. DATA REPORTING Marvell shall make available to Intel the quality data on a regular basis, but no less frequently than monthly. Such data may include yield information, OQA (Outgoing Quality) data, FA details etc. The data is to be sent to the attention of the Intel's Quality Engineer on a monthly basis or mutually agreed upon timeframe. Marvell and Intel may jointly determine that some of the above data reporting is no longer needed once a certain confidence level is reached. Therefore, some of the above data reporting will only be required in the early stages of a program while some will be required on an ongoing basis. This is dependent on the maturity and health of individual Items. QUALITY ASSURANCE REQUIREMENTS Page 2 40 INTEL CONFIDENTIAL 1.7. QUALITY IMPROVEMENT AND CORRECTIVE ACTIONS Upon request from either party, Intel and Marvell will meet to discuss reported data, DPM, and quality improvement plan if the quality levels are not being met. As required, increased frequency of reporting and/or additional corrective actions will be assigned and monitored. Intel may issue a Corrective Action Request if: a) the DPM consistently fails to meet the required DPM or b) Intel or an Intel customer experiences a failure or c) data exists to suggest a risk of impact to Intel or Intel's customers If Corrective Action is requested, Marvell must formally respond within ***** working days after receipt and report any containment action taken. Marvell will provide final failure analysis, root cause and a corrective action plan within ***** calendar days of notification on all returned defective material. If Marvell cannot consistently meet Intel's quality requirements, Marvell must take appropriate steps to improve quality. This may require modification of processes involving manufacturing, material handling, test, etc or other quality requirements as stated in this Exhibit. The stated quality requirements shall not be amended during the term of this Agreement except pursuant to written amendment, signed by both Intel/Marvell. 1.8. PACKAGING REQUIREMENTS Marvell agrees to provide packaging for the products that meets Intel's standard requirement for packaging, labeling etc. 1.9. QUALITY ACTION NOTIFICATION (QAN) AND MARVELL EXCURSIONS A QAN is a process that provides formal management of quality excursions. This is a high visibility process and will take priority over all sustaining issues. Marvell is expected to participate in conference calls and provide written documentation regarding the following focus areas: a) Containment and quarantine b) Root cause analysis c) Corrective actions Marvell commits to proactive notification to Intel of any quality or reliability issues that pose a risk of impact to Intel or Intel's customers. 1.10. RMAS, TRACEABILITY, TRACKING, AND FAILURE ANALYSIS Marvell will provide failure analysis on any failing units returned by Intel or any of Intel's customers. First level failure analysis (Go/ No Go) will be performed within ***** working days of receipt. Final failure analysis (root cause, corrective action) will be performed within ***** calendar days of receipt. The final failure analysis is considered complete when a report is received and accepted by the Intel Item Quality Engineer. Items must be traceable to date, location, and line of manufacture. Item undergoing failure analysis at Marvell or Marvell's suppliers must be tracked sufficiently to provide status updates upon request from Intel. QUALITY ASSURANCE REQUIREMENTS Page 3 41 INTEL CONFIDENTIAL EXHIBIT F SUPPORT REQUIREMENTS General Intel and Marvell shall provide Technical Support at least during normal business hours 8:00 a.m. - 5:00 p.m. PST. Each party shall assign a Program Manager or support specialist to act as a primary contact with respect to technical support provided by each party as described herein. SCOPE OF SUPPORT Support will include training, support services, bug fixes, and the delivery to Intel of all Updates and other enhancements to the Integrated Gb Silicon. Marvell shall provide its standard product support to the Marvell Gb Phy. Intel's support will include training, support services, bug fixes, and the delivery to Marvell of all Updates and other enhancements to the Intel *****, as it pertains to the Integrated Gb Silicon. 1. TRAINING 1.1 Marvell will conduct two (2) Training Classes ("Training Classes"), of 1-day duration each, covering the use of the Marvell Integration Technology, one in ***** and one in *****. Intel will conduct one (1) Training Classes of 1-day duration covering the use of the Intel ***** in Sunnyvale, CA. An initial Training Class will be held by each party at a mutually acceptable date within three months of the Effective Date. The Training Classes shall pertain only to that subject matter related to the Integrated Gb Silicon. 1.2 Prior to each class, Marvell and Intel shall mutually agree on the specific topics to be covered and specific type of training to be provided. 2. SUPPORT SERVICES Marvell shall provide technical support to Intel, which shall include answering questions, via phone and email or on-site at Intel. Such assistance will be available to Intel personnel throughout the term of the Agreement during Marvell's normal business hours as set forth above. Intel shall provide technical support to Intel, which shall include answering questions, via phone and email or on-site at Intel. Such assistance will be available to Marvell personnel throughout the term of the Agreement during Marvell's normal business hours as set forth above. Such support and assistance shall be restricted to that subject matter related to the Integrated Gb Silicon. 2.1 Scope of Support Detail (a) Marvell shall provide to Intel, technical Support for each Marvell Gb Phy release, Integrated Gb Silicon and use of the Marvell Integration Technology. (b) Marvell shall provide to Intel Debugging and Error Correction Support for the Integration of the Marvell Gb Phy and the Intel *****. (c) Bug Fixes or Updates to the Marvell Integration Technology that Marvell develops or distributes, to be delivered to Intel no later than to any of Marvell's other licensees. (d) Integration support as required by the Exhibit D. 2.2 On-site Support For Intel's facilities based within the continental USA, Support shall include reasonable on-site support as required to meet the milestones set forth in Exhibit D. For Intel's facilities based outside of Continental USA, Marvell agrees to provide such on-site support, subject to reasonable notice by Intel and provided that Intel agrees to pay all actual and reasonable travel and normal business expenses of Marvell, plus ***** for each of the first 3 days and ***** thereafter for continuous days of on-site support in support of the ***** SOW. SUPPORT REQUIREMENTS Page 1 42 INTEL CONFIDENTIAL For the Critical level issues as defined below, Marvell agrees to provide on-site support within 48 hours or use its commercially reasonable efforts to provide support as soon as possible thereafter at Intel's sites in the USA, Europe & Middle East. 3. SUPPORT TERM Marvell shall provide Support as set forth in this Schedule F for the period of the Agreement. 4. ADDITIONAL SERVICES If Intel requests any other Support not covered by this Agreement the requested Support shall be provided upon terms and conditions mutually agreed by the parties in writing. 5. PERFORMANCE Marvell represents and warrants that the training and Support described in this Exhibit D will be provided in a workmanlike manner and meet Support Requirements below. SUPPORT PROCESS Technical support is based on three levels of support. Intel shall provide first and second level support to Intel customers. Marvell shall provide third level support to designated Intel engineers. Level 1 Support shall mean that level of support whereby the supporting party (Intel) provides the primary interface through direct communication with its licensees/customers concerning Errors. The provider of Level 1 support will use reasonable commercial efforts to accomplish problem determination (and resolution) when Errors are reported. Level 2 Support shall mean that level of support whereby the supporting party (Intel) undertakes reasonable commercial efforts to re-create and identify the Errors reported to it by its licensees/customers and to provide written documentation (and Error classification as defined below) of such Errors to the provider of Level 3 Support (Marvell) with failure analysis data and test case that will enable the Level 3 Support provider to re-create the reported Error. In addition, the Level 2 Support provider will search any problem database supplied by the Level 3 Support provider, for known Errors and provide existing Updates to its licensees should they exist. Level 3 Support shall mean the level of support whereby the supporting party (Marvell) undertakes reasonable commercial efforts to correct Errors and tests and delivers validated fixes in response to requests from the provider of Level 2 Support where Level 2 Support has exercised reasonable commercial efforts to re-create and identify the Errors reported to it. Level 3 Support includes updating any relevant problem database to identify Updates to known Errors. Level 3 Support shall also provide technical guidance to Level 2 Support as appropriate to assist Level 2 Support in resolving future Errors for their customers/licensees. ERROR CLASSIFICATION These classifications are determined by Intel as it relates to the support of its customers. Critical Means Errors which left unresolved will severely impact a customer's ability to ship products based on Intel Product. Major Means Errors which cause a material deviation in performance and/or functionality from the Intel Product specification. Minor Means Errors which do not cause a material deviation in performance and/or functionality from the Intel Product. RESPONSE TIME OBJECTIVE Marvell will use reasonable commercial efforts to provide Intel with a written or electronic acknowledgement of Intel's Error notification within 24 hours after the receipt of such Error notification. SUPPORT REQUIREMENTS Page 2 43 INTEL CONFIDENTIAL The following time frames shall be used to specify response time objectives for each type of Error. The targeted time frame below is defined from the time that Intel provides written notification to Marvell, to the time that Marvell provides an acceptable resolution to Intel. The parties understand that the targeted response times below may not be able to be achieved, depending upon the kind of Error. Critical ***** Major ***** Minor ***** ADDITIONAL RESPONSE OBJECTIVES 1. Marvell will make reasonable commercial efforts to provide selected bug/errata reports to Intel within ***** Business Days of Marvell's verification of each bug/errata for the Integrated Gb Silicon and those reported to Marvell by customers other than Intel for the Marvell Gb Phy. Similarly, Marvell will make available to Intel any related work-arounds and engineering releases containing fixes after they become available. 2. Intel will make reasonable commercial efforts to provide selected bug/errata reports to Marvell within ***** Business Days of the Intel's verification of each bug/errata for the Integrated Gb Silicon. Similarly, Intel will make available to Marvell any related work-arounds and engineering releases containing fixes after they become available. SUPPORT REQUIREMENTS Page 3